The ADC/ADC/ADC/ADC are 8-bit successive approximation A/D converters Details, datasheet, quote on part number: ADC ADC/ADC/ADC/ADC 8-Bit High-Speed Serial I/O A/D products and disclaimers thereto appears at the end of this data sheet. An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical the end of the data sheet. .. ADC
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IRE TM serial data exchange standard for easy interface to the. For devices offering guaranteed voltage ref. The analog inputs can be configured to operate in various. In addition, input voltage spans. Remote sensing in noisy environments. No missing codes over temperature. Dxtasheet Maximum Ratings Notes 1, 3. Operating Ratings Notes 2, 3.
Distributors for availability and specifications. Supply Voltage V CC. Voltage at Inputs and Outputs. Input Current at Any Pin Note 4. Package Input Current Note 4.
ESD Susceptibility Note 6. N Package 10 sec. Vapor Phase 60 sec. Logical “1” Input Voltage. Logical dafasheet Input Voltage.
Logical “1” Input Current. Logical “0” Input Current. Logical “1” Output Voltage. Logical “0” Output Voltage. Conversion Time Not Including. Data Valid Note Capacitance of Logic Inputs.
Capacitance of Logic Outputs. Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions datasheef which the device is functional. These ratings do not guarantee specific performance limits. The guaranteed specifications apply only for the test conditions listed. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins.
Human body model, pF capacitor discharged through a 1. C and represent the most likely parametric norm. Total unadjusted error includes offset, full-scale, linearity, multiplexer. Cannot be tested for the ADC Two on-chip diodes are tied to each analog input see Block Diagram which will forward-conduct for. During testing at low V CC levels e. Datasheey spec allows 50 mV. Channel leakage current is measured after a single-ended channel is selected and the clock is turned off.
For off channel adc080031 current the following two. In the case that an available clock has a duty cycle outside of these limits. The maximum time the clock can be high or low is ? Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in see Block Diagram to allow.
Power Supply Current vs. Leakage Current Test Circuit. Otherwise these devices are compatible with industry. LSB information is maintained for remainder of clock periods until CS goes high. A unique input multiplexing scheme has been utilized to pro. The design of these converters utilizes a comparator struc. The actual voltage converted is always the difference be. One converter package can now handle ground refer. The polarity of each input terminal of the pair indicates which. A particular input configuration is assigned during the MUX.
MUX address selects which of the analog inputs are to be.
This voltage does not have to be analog ground; it. This feature is most useful in single-supply applica. Differential inputs are restricted to adjacent channel pairs. For example, channel 0 and channel 1 may be selected as a. In addition to selecting differential.
Channel 0 may be. This programmability is best illustrated by. Because the ADC contains dattasheet one differential input. In this mode the voltage. Adc0031 the input configuration is under software control, it can. To understand the operation of these converters it is best to.
National Semiconductor – datasheet pdf
The analog input voltages for each channel can range from. A conversion is initiated by pulling the CS chip select. This line must be held low for the entire conver. The converter is now waiting for a start bit and its. A most important characteristic of these converters is their. On each rising edge of the clock the status of the data in. DI line is clocked into the MUX address shift register. The start bit is the first logic “1” that appears on this line. Following the start bit the.
ADC08031 Datasheet PDF
The stored data in the successive approximation register. When the start bit has been shifted into the start location. SE is forced low the data is clocked out LSB first. The SARS line goes high at this time to signal that a con. LSB first, is automatically shifted out the DO line after. The DO line then goes low.
ADC 데이터시트(PDF) – National Semiconductor (TI)
All internal registers are cleared when the CS line is high. During the conversion the output of the SAR comparator. See Data Input Tim. If another conversion is de. The DI and DO lines can be tied together and controlled.
This data is the result of the conver. This is possible because the DI input is only “looked-at”. After 8 clock periods the conversion is completed.
For absolute accuracy, where the analog input varies be. The voltage applied to the reference input on these convert.
F capacitor is recommended. The LM and LM The devices can be used. The reference pin must be connected to a. The maximum value of the reference is limited to the V CC. This pin is the top of a. The minimum value, however, can be quite. Particular care must be taken with regard to.
In a ratiometric system the analog input voltage is propor.